Distinguished Lecturers

Dr. Adar Kalir is Director of Manufacturing Science Systems within  the Fab and Sort Manufacturing (FSM) network in Intel’s Manufacturing, Supply-chain and Operations (MSO) group. He is the lead engineer in FSM for Intel’s 10nm super-fin and Intel 7 products and is responsible for development of models and processes that enable factory productivity, output, cost, and cycle-time in startup, ramp, and high-volume manufacturing (HVM) across Intel's global manufacturing network. He has published over 110 technical papers, including IEEE Trans. on Semiconductor Manufacturing Best Paper Award in 2019. He also serves as an Adjunct Associate Professor at Ben-Gurion University (BGU), Israel, and as a Co-chair of the IEEE Technical Committee on Semiconductor Manufacturing Automation (TC- SMA).

Talk #1

On Manufacturing Science and Challenging Problems in Semiconductor Manufacturing

The semiconductor manufacturing process is likely the most complex manufacturing process that has ever been devised. It is characterized by extremely high cost of machines and equipment (~40%); very long production processes (100’s of process steps); continuously tighter control limits on inline parametrics, hence high variability (50% CoV’s > 2); high re-entrance (‘job-shop’ like) coupled with ‘flow line’ production management; and high mix of products. It is no surprise, therefore, that this environment also presents challenging problems to manufacturing practitioners, ranging from long-term strategic planning and supply-chain management, all the way down to challenging and uniquely constrained scheduling and dispatching problems at the shop-floor level. A few examples of such challenging problems shall be described – and practical implementable solutions to these problems will be reviewed. Specifically, the topics of production cycle time reduction via effective controls, opportunities for Preventive Maintenance (PM) improvements, and capital savings via optimal allocations of testing equipment are discussed as leading examples.

Talk #2

Maximizing Output During Ramp by Integrating Capacity and Velocity

In the semi-conductor industry, factories ramp their production capacity in parallel with tool (machine) installations. Ramp capacity, and subsequently wafer starts, are aligned with additional installs of the most expensive tool. Subsequently, starts are set to the full capacity of that limiting toolset. We argue that this may not be best method to maximize output over the ramp period and that by keeping ramp starts below constraint capacity, increased levels of cumulative output can be achieved for a desired planning horizon (e.g., the first year of production). A mathematical framework of the problem is provided to support our hypothesis, together with numerical examples and a set of simulation experiments.

Yan Qiao (M’16-SM’21) received the B.S. and Ph.D. degrees in Industrial Engineering and Mechanical Engineering both from Guangdong University of Technology, Guangzhou, China, in 2009 and 2015, respectively. From Sep. 2014 to Sep. 2015, he was a Visiting Student with the Department of Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, NJ, USA. From Jan. 2016 to Dec. 2017, he was a Post-Doctoral Research Associate with the Institute of Systems Engineering, Macau University of Science and Technology, Macao. Since Jan. 2018, he is an Assistant Professor at the Institute of Systems Engineering, Macau University of Science and Technology, Macao. He has over 80 publications, including one book chapter and 30+ regular papers in IEEE Transactions. Besides, he was a recipient of QSI Best Application Paper Award Finalist of 2011 IEEE International Conference on Automation Science and Engineering, Best Student Paper Award of 2012 IEEE International Conference on Networking, Sensing and Control, Best Conference Paper Award Finalist of 2016 IEEE International Conference on Automation Science and Engineering, Best Student Paper Award Finalist of 2020 IEEE International Conference on Automation Science and Engineering, 2021 Hsue-shen Tsien Paper award of IEEE/CAA Journal of Automatica Sinica, and Best Paper Award in Application of 2022 IEEE International Conference on Networking, Sensing and Control. He has served as a reviewer for a number of journals. His research interests include scheduling and optimization, semiconductor manufacturing systems, and smart manufacturing.

Talk #1 

Real-time control policy for time-constrained single-arm cluster tools with activity time variation

With wafer residency time constraints, to obtain a feasible schedule for cluster tools is to balance the wafer sojourn time to some extent among the processing steps. However, the wafer sojourn time fluctuation caused by activity time variation can result in the violation of residency time constraint at some step such that a feasible schedule under the assumption of deterministic activity times may become infeasible. Thus, it is a great challenge to operate a cluster tool subject to wafer residency time constraints and activity time variation. This topic introduces the real-time operation issues of single-arm cluster tools. In this topic, we show that the system is modeled by a Petri net; with this model, a real-time control policy is proposed to offset the activity variation as much as possible by dynamically adjusting the robot waiting times. In this way, an off-line schedule under deterministic activity times is made to be adaptable to certain activity time disturbance such that it becomes feasible. An illustrative example is given to show the applications of the work.

Talk #2

Scheduling of cluster tools with strict wafer residency time constraints and chamber cleaning requirements

Cluster tools have played a significant role in the entire process of wafer fabrication. As the width of circuits shrinks down to less than 10nm, strict operational constraints are imposed on the operations of cluster tools in order to ensure the quality of processed wafers. Particularly, wafer residency time constraints and chamber cleaning requirements are commonly seen in etching, chemical vapor deposition, etc. They make a scheduling problem of cluster tools more challenging. This topic introduces the scheduling analysis for cluster tools with wafer residency time constraints and chamber cleaning requirements. To solve such a challenging problem, a novel virtual wafer-based scheduling method is proposed. By this method, under a steady state, a process module (PM) processes either a real or virtual wafer at a time. When a PM processes a virtual one, its chamber may perform a cleaning operation. In this way, we can meet not only the strict residency time constraints for real wafers, but also innovatively meet chamber cleaning requirements. Based on such a novel scheduling method, an efficient binary integer programming model is established to optimize the throughput of cluster tools. Experimental results show the efficiency and effectiveness of the proposed method.

Talk #1 

Transforming Manufacturing Industry from Automation to Intelligenization with Industry 4.0 Technologies

Industry 4.0 intends to address a fast-changing and challenging manufacturing environment with diverse demands, short order leadtime and product life cycle, limited capacities, and highly complex process technologies. A manufacturing system integrated with Industry 4.0 technologies, such as AI, machine learning, big data analytics, digital twin, and Internet of Things, is capable of performing real-time monitoring and optimization of manufacturing processes in various aspects from high level strategic resource and production planning down to real-time equipment-level smart dispatching and predictive maintenance. By fully using real-time data and AI, the system is able to help manufacturers shorten production and R&D processes, increase production capacity, reduce production cost, guarantee product quality, and improve product yield. It is suitable to help not only high-tech industries such as semiconductor wafer fabrication, but also conventional labor-intensive sectors. This talk illustrates the transformation of semiconductor manufacturing activities from automation to intelligenization by using Industry 4.0 technologies through real-life wafer fabrication applications.

Talk #2

Modeling, Scheduling and Real-time Control of Cluster Tools in Semiconductor Manufacturing

This talk intends to present Petri nets as a modeling, analysis, optimal scheduling and real-time control tool for single and multicluster tools that are widely used in semiconductor manufacturing industry. We illustrate how to use Petri nets to model various wafer production features involved in these highly expensive robotic manufacturing systems. Then we show how to use the resultant Petri net models to establish various schedulability conditions and derive extremely efficient algorithms that can compute optimal schedules for single and multi-cluster tools. When the bounded variation of activity time is caused in a fabrication process, we finally demonstrate how to adjust the scheduled robot wait time to offset such variation in order to achieve desired real-time optimal execution results. Our work focuses on those process-bounded cluster tools in which robots are fast enough such that they have some idle time in realizing an optimal schedule.